LOGIC DE/ DIGITAL engineerOpen Nationals

Petaling, Selangor 14 April (updated)

Chis International Technical Resource Sdn Bhd

  • Description

    LOGIC DE/ DIGITAL engineer
    Kuala Lumpur Malaysia
    Permanent and Contract
    Open for Malaysians and Foreigners
    Salary is negotiable

    We are looking for potentials to join us to strengthen our DFx design and validation competency.
    Candidates will have the opportunity to learn and work on:
    o Scan RTL architecture, design and methodology
    o Perform scan coverage analysis and debug with Spyglass-DFT or other ATPG tools
    o Scan RTL and GLS test validation to ensure quality design
    o generate test patterns using industry standard tools, analyze and drive the improvements to test coverage
    o providing DFT constraints/exceptions to Static Timing Analysis (PV) and coordination of Scan/ATPG collaterals with IP provider
    o responsible for design/testing other part of design, including memory, mized signal, IO, custom LBIST + MBIST, 1149.1 JTAG.
    o Partnership with post-Silicon High Volume Manufacturing (HVM) Team to enable Scan DFT test capability
    o Collaborate with various stakeholders in architecture, IP, structural design, SoC RTL, and post-Silicon teams
    o understand DFT/Test architectures, integrate DFT infrastructure (TAP controller, Bscan, debug capability, loopback, pattern generator) into IP/SOC
    o implement DFT/Test in designs in the area of DFT Synthesis

    • Requirement :
    o 8 years' experience in implementing DFT/Test in designs
    o Understanding of DFT Infra, ATPG process, scan compression, MBIST,..
    o Knowledge in RTL integration and validation methodologies
    o Understanding of Scan/ATPG collaterals
    o Familiar with Scan design, methodology, coverage analysis and test validation
    oTcl/Tk/Perl to automate design process and improve efficiency
    o Knowledge of Synthesis/Scan stitching, STA, ATPG and MV design an advantage
    o Knowledge of Synopsys DC/DFT Compiler, Primetime and UPF an advantage
    o Familiar with UNIX, and well-versed in Verilog or C Programming
    o independent problem solving, debugging various simulation failures, formal verification etc.
    o Ability to communicate well with counterparts and key stakeholders including cross-site partners
  • Number of vacancies: 5

    • Requirements

  • Minumun level of education: Bachelor´s Degree
  • Years of experience: 10
  • Language(s): English
  • Availability for travel: Yes
  • Availability for change of residence: Yes

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