Senior Staff STA or Structural or Physical Design EngineerOpen Nationals based in Malaysia

Petaling, Selangor 14 April (updated)

Chis International Technical Resource Sdn Bhd

  • Description

    Senior Staff STA / Structural / Physical Design Engineer
    Kuala Lumpur Malaysia
    Permanent and Contract
    Open for Malaysians and Foreigners
    Salary is negotiable

    Description:
    MIG MYS is seeking senior structural design engineers to join our talented and vibrant team. You will be directly involved in delivering next-generation LPDDR5/DDR5 PHY or Die2Die Interconnects PHY designs for SOC application on Intel’s leading process node.

    Key Responsibilities for this position includes but not limited to:
    - Lead & Manage a group of Static Timing Analysis(STA)/Performance Validation(PV) engineers
    - Working closely with Architecture and Design team to understand, define & generate timing specification/constraints
    - Drive Implementation requirements (ie Clock Tree Synthesis targets), Influence & Continuous seek to improve the Timing Closure methodology, etc
    - Drive timing closure, execute STA using industry tool (Primetime) and perform various quality check to ensure design converges on the timing signoff requirements.
    - Analyze timing report and proficient in using script to debug, automate tasks and provide timely feedback for timing ECO.
    - Define and develop I/O budgets and drive for IP budget convergence.
    - Possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.

    Qualifications:
    You should possess a relevant educational qualification, BSEE or equivalent with 8+ years/MSEE or equivalent with 6+ years design experience in the structural/physical design domain. Additional qualifications include:
    - Have multiple tape-out experience in deep submicron, preferably experience in 14nm and below
    - Must have in depth, extensive knowledge and hands-on experience in Static timing analysis and timing signoff, including SDC development and timing budgeting.
    - Experience in relevant VLSI structural/physical design methodology, flows and relevant EDA tools will be an advantage
    - Experienced in industry STA tools: Primetime and Primetime SI
    - Hands-on expertise with scripting languages such as Perl, TCL, and knowledge of hardware description languages of VHDL & Verilog.
    - Experience of mentoring junior team members and charting their development for success.
  • Number of vacancies: 5
  • Requirements

  • Minumun level of education: Bachelor´s Degree
  • Years of experience: 6
  • Language(s): English
  • Availability for travel: Yes
  • Availability for change of residence: Yes

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